The concept of switching matrices is not new. For many years matrices have been used to interconnect telephone subscribers to one another and more recently they have been used to interconnect processors and memories in a computer processor system. In the processor world time and speed become critical. Thus, there is a constant effort to combine more and more processing power into less and less space.
As this unrelenting push for small size and increased computing power continues, the interconnections between system components become more and more sophisticated. One example of the problem arises in imaging systems which obtain visual images and perform various manipulations with respect to the data and then control the display of the imaged and stored data inherently requiring large amounts of computations and memory. Such imaging systems are prime candidates for multi-processing where different processors perform different tasks concurrently in parallel. These processors can be working together in the single instruction, multiple data mode (SIMD) where all of the processors are operating from the same instruction but obtaining data from various sources, or the processors can be working together in the multiple instruction, multiple data mode (MIMD) where each processor is working from a different set of instructions and working on data from different sources. For different operations, different configurations are necessary.
Contention is a problem when several processors, or other devices, try to access the same memory space. Typically, a central processor or a standalone logic circuit, monitors the contending processors and allows one processor at a time to have access to a given memory space. When time and space is at a premium, this is difficult to achieve. In addition, any standalone contention system would require connections for moving data back and forth and thus would require space for the movement of this data thereby compounding the problem.
There is thus a need in the art for a system which handles multi-processors having multi-memories such that the address space from all of the memories is available to one or more processors concurrently even when the processors are handling different instruction sets.
There is a further need in the art for a multi-processing system which is constructed with a switch capable of allowing both SIMD and MIMD operations on an interchangeable basis.
One method of solving the huge interconnection problem in complex systems such as the image processing system shown in one embodiment of the invention is to construct the entire processor as a single device. Conceptually this might appear easy to achieve, but in reality the problems are complicated.
First of all, an architecture must be created which allows for the efficient movement of information while at the same time consuming a minmum amount of precious silicon chip space in order to achieve a high performance to cost ratio. The architecture must allow a very high degree of flexibility since once fabricated, it cannot easily be modified for different applications. Also, since the processing capability of the system will be high, there is a need for high bandwidth of each data input/output signal which moves information on and off the chip. This is so since the physical number of leads which can attach to any one chip is limited.
It is also desirable to design an entire parallel processor system, such as an image processor, on a single silicon chip while maintaining the system flexible enough to satisfy wide ranging and constantly changing operational criteria.
It is further desirable to construct such a single chip parallel processor chip where the processor memory interface is easily adaptable to operation in various modes, such as SIMD and MIMD, or both as well as adaptable to efficient on-off chip data communications.